Nuclear physics using radioactive beams has been the most dynamic research area in nuclear science. A High Intensity Heavy-Ion Accelerator Facility (HIAF) is currently under construction, and a cutting-edge High Energy Fragment Separator (HFRS) with high energy and intensity capabilities is being installed. HFRS is an important facility in the HIAF, located between BRing and SRing, with a total length of 180 m. It is designed to study the properties of rare isotopes and their nuclear reactions relevant to astrophysics. HFRS is characterized by high magnetic rigidity, large optical acceptance of ions, and accurate particle identification. HFRS identifies particles using time-of-flight measurements, position measurement and energy loss measurement from multi-detector cooperation can identify isotopes with mass numbers up to 200. HFRS provides accurate energy loss measurement with multiple sampling ionization chambers, time measurement with diamond detectors and position resolution with GEM-TPC detectors. High-precision clock generation and distribution is a prerequisite for these detectors to work together to accurately measure particle motion time intervals and position resolution for accurate particle identification. It also helps to correlate and align data from different channels of different detectors along the time axis to construct particle trajectories and restore physical phenomena accurately. This paper describes the prototype design of high-precision clock generation and distribution for multiple detectors in HFRS at HIAF. The system is based on a master-slave architecture design. The master board generates a high-precision 40 MHz clock through a high-quality crystal oscillator. Then, it feeds it to the input of a low-jitter clock fan-out chip, which can distribute the 12 LVPECL level signal outputs to the optical transceivers and then transmit to the slave boards via optical links. The slave board receives the clock signals from the master board, then fans out 10 LVDS differential clock signals through a low jitter clock chip, and provides synchronized clock signals to the front-end electronics or DAQ system through the differential LEMO connectors. The test results indicate that the time interval error (TIE) jitter is better than 3 ps, and the cycle-to-cycle period (C-C period) jitter is better than 8.7 ps after transmission over 200 m optical fiber. The system can provide a stable and accurate 40 MHz synchronous clock to meet the design requirements.
 

Clock generation and distribution,High-precision clock,HFRS,HIAF